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L6726A
Single phase PWM controller
Feature

Flexible power supply from 5V to 12V Power conversion input as low as 1.5V 1% output voltage accuracy High-current integrated drivers Adjustable output voltage 0.8V internal reference Sensorless and programmable OCP across Low-side RdsON Oscillator internally fixed at 270kHz Programmable soft-start LS-LESS start up Disable function FB disconnection protection SO-8 package SO-8
Description
L6726A is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general DC-DC converters by using a compact SO-8 package. Device flexibility allows managing conversions with power input VIN as low as 1.5V and device supply voltage ranging from 5V to 12V. L6726A provides simple control loop with transconductance error amplifier. The integrated 0.8V reference allows regulating output voltage with 1% accuracy over line and temperature variations. Oscillator is internally fixed to 270kHz. L6726A provides programmable over current protection. Current information is monitored across the Low-Side mosfet RdsON saving the use of expensive and space-consuming sense resistors. FB disconnection protection prevents excessive and dangerous output voltages in case of floating FB pin.
Applications

Subsystem power supply (MCH, IOCH, PCI...) Memory and termination Supply CPU & DSP power supply Distributed power supply General DC / DC converters
Table 1. Device summary
Order codes L6726A L6726ATR Package SO-8 SO-8 Packaging Tube Tape & Reel
July 2007
Rev 3
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Contents
L6726A
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 6.2 Low-Side-Less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 7.2 7.3 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.1 Over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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L6726A
Contents
8
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1 8.2 8.3 8.4 8.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soft Start time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Embedding L6726A-based VRs... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Typical application circuit and block diagram
L6726A
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VIN = 1.5V to 19V (1)
CDEC
5 6
D
VCC = 5V to 12V
VCC
FB
BOOT
1
RD
CBOOT
L6726A
7
COMP / DIS
UGATE
2
RgHS
CHF
CBULK
HS L
Vout
CF RFB
ROS CP
PHASE
8
RF
3
GND
LGATE / OC
4
RgLS
LS
RSN
COUT
ROCSET
CSN
LOAD
L6726A Reference Schematic (1) Up to 12V with Vcc > 5V
1.2
Block diagram
Figure 2. Block diagram
VCC
OCP CONTROL LOGIC & PROTECTIONS
VOCTH
ISS
BOOT
DISABLE
ADAPTIVE ANTI CROSS CONDUCTION
HS
UGATE PHASE
CLOCK
S R
Q
PWM
VCC
OSCILLATOR
TRANSCONDUCTANCE ERROR AMPLIFIER + -
LS
LGATE / OC GND
L6726A
COMP / DIS FB
0.8V IOCSET
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L6726A
Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 3. Pins connection (top view)
BOOT UGATE GND LGATE / OC
1 2 3 4
8 7
L6726A
6 5
PHASE COMP / DIS FB VCC
2.1
Pin descriptions
Table 2. Pins descriptions
Pin n Name Function HS Driver Supply. Connect through a capacitor (100nF) to the floating node (LS-Drain) pin and provide necessary bootstrap diode from VCC. HS Driver Output. Connect to HS mosfet gate. All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane.
1 2 3
BOOT UGATE GND
4
LGATE. LS Driver Output. Connect to LS mosfet gate. OC. Over Current threshold set. During a short period of time following VCC rising over UVLO threshold, a 10A current is sourced from this pin. Connect to GND with an ROCSET resistor greater than 5k to program OC LGATE / OC Threshold. The resulting voltage at this pin is sampled and held internally as the OC set point. Maximum programmable OC threshold is 0.55V. A voltage greater than 0.75V (max) activates an internal clamp and causes OC threshold to be set at 400 mV. ROCSET not connected sets the 400mV default threshold. VCC Device and LS Driver power supply. Operative range from 4.1V to 13.2V. Filter with at least 1F MLCC to GND. Error Amplifier Inverting Input. Connect with a resistor RFB to the output regulated voltage. Additional resistor ROS to GND may be used to regulate voltages higher than the reference.
5
6
FB
7
COMP. Error Amplifier Output. Connect with an RF - CF // CP to GND to compensate the device control loop in conjunction to the FB pin. During the Soft-Start phase, a 10A current is sourced from this pin so the COMP / DIS compensation capacitors also act to program the SS time. DIS. The device can be disabled by pulling this pin lower than 0.4V (min). Setting free the pin, the device enables again. HS Driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RdsON drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS mosfet is OFF.
8
PHASE
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Pins description and connection diagrams
L6726A
2.2
Thermal data
Table 3. Thermal data
Symbol RthJA TMAX TSTG TJ Parameter Thermal resistance junction to ambient(1) Maximum junction temperature Storage temperature range Junction temperature range Value 85 150 -40 to 150 -20 to 150 Unit C/W C C C
1. Measured with the component mounted on a 2S2P board in free air (6.7cm x 6.7cm, 35m (P) and 17.5m (S) copper thickness).
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L6726A
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol VCC VBOOT VUGATE to GND to PHASE to GND to PHASE to PHASE; t < 50ns to GND to GND to GND to GND; t < 50ns FB, COMP to GND
1. ESD immunity for FB pin is guaranteed up to 1000V (Human Body Model)
Parameter (1)
Value -0.3 to 15 15 45 -0.3 to (VBOOT - VPHASE) + 0.3 -1 VBOOT + 0.3 -8 to 30 -0.3 to VCC + 0.3 -2.5 -0.3 to 3.6
Unit V V
V V V V
VPHASE VLGATE
3.2
Electrical characteristics
Table 5. Electrical characteristics (VCC = 12V; TA = -20C to +85C unless otherwise specified).
Symbol Parameter Test conditions Min. Typ. Max. Unit
Recommended operating conditions VCC VIN Device supply voltage See Figure 1 13.2 Conversion input voltage VCC < 7.0V 19.0 V V 4.1 13.2 V
Supply current and power-ON ICC IBOOT UVLO VCC supply current BOOT supply current VCC Turn-ON Hysteresis Oscillator FSW VOSC dMAX Main oscillator accuracy PWM ramp amplitude Maximum duty cycle 80 TA = 0C to +70C 243 225 270 270 1.1 297 kHz 315 V % UGATE and LGATE = OPEN UGATE = OPEN; PHASE to GND VCC Rising 0.2 6 0.5 4.1 mA mA V V
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Electrical specifications Table 5. Electrical characteristics (continued) (VCC = 12V; TA = -20C to +85C unless otherwise specified).
Symbol Reference Output voltage accuracy Transconductance error amplifier gm IFB A0 F0 ICOMP Transconductance(1) Input bias current Open loop gain(1) Unity gain(1) Source current Current capability Sink current Soft-Start and disable ISS DIS Gate drivers IUGATE RUGATE ILGATE RLGATE HS source current HS sink resistance LS source current LS sink resistance BOOT - PHASE = 5V to 12V BOOT - PHASE = 5V to 12V VCC = 5V to 12V VCC = 5V to 12V 1.5 1.1 1.5 0.65 Soft-start current Disable threshold From COMP pin COMP falling 0.4 10 0.5 -360 Sourced from FB 100 70 4 360 5 VOUT = 0.8V, TA = 0C to 70C VOUT = 0.8V -1 -1.5 1 Parameter Test conditions Min. Typ. Max.
L6726A
Unit
% 1.5
mS nA dB MHz A A
A V
A A
Over-current protection IOCSET VOC_SW OCSET current source OC switch-over threshold Sourced from LGATE pin. See Section 7.1.1 VLGATE/OC rising VPHASE to GND -400 10 780 A mV mV
VOCTH_FIXED Fixed OC threshold
1. Guaranteed by design, not subject to test.
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L6726A
Device description
4
Device description
L6726A is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 8-pin device allows reducing cost and size of the power supply solution. L6726A is designed to operate from a 5V or 12V supply bus. Thanks to the high precision 0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8V with 1% accuracy over line and temperature variations (between 0C and +70C). The switching frequency is internally set to 270kHz. This device provides a simple control loop with externally compensated transconductance error-amplifier and programmable soft start. Low-Side-Less feature allows the device to perform soft-start over pre-charged output avoiding negative spikes at the load side. In order to avoid load damages, L6726A provides programmable threshold over current protection. Output current is monitored across Low-Side MOSFET RdsON, saving the use of expensive and space-consuming sense resistor. L6726A also features FB disconnection protection, preventing dangerous uncontrolled output voltages in case of floating FB pin.
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Driver section
L6726A
5
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition. The driver for high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode:

to check for high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied; to check for low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitation and recommended operating conditions) can be chosen freely.
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L6726A
Driver section
5.1
Power dissipation
L6726A embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers power.
Device Bias Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
P DC = V CC ( I CC + I BOOT )
Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency, the voltage supply of the driver and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results:
P SW = F SW [ Q gHS ( V BOOT - V PHASE ) + Q gLS V CC ]
where VBOOT - VPHASE is the voltage across the bootstrap capacitor. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. Figure 4. Soft start (left) and disable (right)
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Soft start and disable
L6726A
6
Soft start and disable
L6726A implements a soft start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. The device sources a 10A soft start current from COMP, linearly charging the compensation network capacitors. The ramping COMP voltage is compared to the oscillator triangular waveform generating PWM pulses of increasing width that charge the output capacitors. When the FB voltage crosses 800 mV, the output voltage is in regulation: soft start phase will end and the transconductance error amplifier output will be enabled closing the control loop. In the event of an over current during soft start, the over current logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates. This condition is latched, cycle VCC to recover. The device sources soft start current only when VCC power supply is above UVLO threshold and over current threshold setting phase has been completed.
6.1
Low-Side-Less start up (LSLess)
L6726A performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoids the dangerous negative spike on the output voltage that can happen if starting over a precharged output and limits the output discharge (amount of output discharge depends on programmed SS time length: the shorter the programmed SS, the more limited the output discharge). If the output voltage is pre-charged to a voltage higher than the final one, the HS would never start to switch. In this case, LS is enabled and discharges the output to the final regulation value. Figure 5. LSLess startup (left) vs. Non-LSLess startup (right)
6.2
Enable / disable
The device can be disabled by pushing COMP / DIS pin under 0.4V (min). In this condition HS and LS MOSFETs are turned off, and the 10A SS current is sourced from COMP / DIS pin. Setting free the pin, the device enables again performing a new SS.
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L6726A
Protections
7
7.1
Protections
Over current protection
The over current feature protects the converter from a shorted output or overload, by sensing the output current information across the Low Side MOSFET drain-source onresistance, RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RdsON current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an Over Current Event is detected. If two Over Current Events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both LS and HS MOSFETs in a latched condition. To recover from Over Current Protection triggered, VCC power supply must be cycled.
7.1.1
Over current threshold setting
L6726A allows to easily program an Over Current Threshold ranging from 50mV to 550mV, simply by adding a resistor (ROCSET) between LGATE and GND. During a short time following VCC rising over UVLO threshold, an internal 10A current (IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as Over Current Threshold. The OC setting procedure overall time length ranges from 5.5ms to 6.5ms, proportionally to the threshold being set. Connecting a ROCSET resistor between LGATE and GND, the programmed threshold will be:
I OCSET R OCSET I OCth = ------------------------------------------R dsON
ROCSET values range from 5k to 55k. If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up inrush current and noise. This can result in undesired OCP triggering. In this case, consider increasing ROCSET value. In case ROCSET is not connected, the device switches the OCP threshold to a 400mV default value: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches 700mV (typ), enabling the 400mV default threshold and suddenly ending OC setting phase. See Figure 6 for OC threshold setting procedure timings picture and oscilloscope sample waveforms.
7.2
Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100nA bias current is always sourced from this pin. If FB pin is not connected, bias current will permanently pull up FB: this forces COMP pin low, avoiding output voltage rising to dangerous levels.
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Protections Figure 6.
L6726A OC threshold setting procedure timings (top) and waveforms (bottom)
ROCSET connected ROCSET not connected
UVLO Th VCC PWM ramp bottom edge Enable Th COMP 700mV LGATE
5.5ms - 6.5ms Setting Procedure tDELAY
UVLO Th VCC PWM ramp bottom edge Enable Th COMP 700mV LGATE
Setting Procedure
tDELAY
7.3
Under voltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device will start up when VCC reaches UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. The 4.1V maximum UVLO upper threshold allows L6726A to be supplied from 5V and 12V busses in or-ing diode configuration. Figure 7. OCP trip, default threshold, LS: STD38NH02L (left). UVLO turn off (right)
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L6726A
Application details
8
8.1
Application details
Output voltage selection
L6726A is capable to precisely regulate an output voltage as low as 0.8V. In fact, the device comes with a fixed 0.8V internal reference that guarantees the output regulated voltage to be within 1% tolerance over line and temperature variations between 0C and 70C (excluding output resistor divider tolerance, when present). Output voltage higher than 0.8V can be achieved by adding a resistor ROS between FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB V OUT = V REF 1 + ---------- R OS
where VREF is 0.8V.
8.2
Compensation network
The control loop shown in Figure 8 is a voltage mode control loop. The error amplifier is a transconductance type with fixed gain (3.3mS typ.). The FB voltage is regulated to the internal reference, thus the output voltage is fixed accordingly to the output resistor divider (when present). Transconductance error amplifier output current generates a voltage across ZF, which is compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. Figure 8. PWM control loop
VIN OSC V OSC
_ + PWM COMPARATOR
L
R COUT ESR
V OUT
OTA COMP CF RF CP + _
VREF FB R FB R OS OUTPUT DIVIDER
ZF
The converter transfer function is the small signal transfer function between the voltage at the output node of the EA (COMP) and VOUT. This function has a double pole (complex conjugate) at frequency FLC depending on the L-COUT resonance and a zero at FESR
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Application details
L6726A
depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC. VOUT is scaled and transferred to FB node by the output resistor divider. The compensation network closes the loop joining FB and COMP node with transfer function ideally equal to -gm*ZF. Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF; however, for stability, it should not exceed FSW/2. To achieve a good phase margin, the control loop gain has to cross 0dB axis with -20dB/decade slope. As an example, Figure 9 shows an asymptotic bode plot of a type II compensation. Figure 9. Example of type II compensation.
Gain [dB] OTA open loop gain closed loop gain compensation gain converter open loop gain 0dB FZ FP
20log (gm*RF ) 20log [VIN/VOSC*ROS/(RFB+ROS)] F0dB FLC FESR Log (Freq)
Open loop converter singularities: a) b)
1 F LC = --------------------------------2 L C OUT 1 F ESR = ------------------------------------------2 C OUT ESR
Compensation Network singularities frequencies: a) b)
1 F Z = -----------------------------2 R F C F 1 F P = ------------------------------------------------CF CP -------------------- 2 R F C F + C P
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L6726A
Application details Type II compensation relies on the zero introduced by the output capacitors bank to achieve stability. Thus, a needed condition to successfully apply type II compensation is F ESR < F 0dB (usually true when output capacitor is based on electrolytic, aluminium electrolytic or tantalum capacitor). To define compensation network components values, the below suggestions may be followed: a) Set the output resistor divider in order to obtain the desired output voltage:
V OUT R FB ---------- = -------------- - 1 R OS V REF
Usual values of RFB and ROS ranges from some hundreds of to some k (consider trade-off between power dissipation on output resistor divider and offset introduced by FB bias current). If the desired output voltage is equal to internal reference, ROS has to be NC and FB pin can be directly connected to VOUT. b) Set RF in order to obtain the desired closed loop regulator bandwidth according to the approximated formula:
F 0dB F ESR V OSC 1 R FB + R OS R F = ------------------------------ ------------------ ------- ---------------------------2 R OS V IN gm F LC
If VOUT = VREF, just consider (RFB+ROS)/ROS factor equal to 1. c) Place FZ below FLC (typically 0.2*FLC):
5 C F = -------------------------------2 R F F LC
d)
Place FP at 0.5*FSW:
CF 1 C P = ---------------------------------------------------- ----------------------------- R F C F F SW - 1 R F F SW
e) f)
Check that compensation network gain is lower than open loop transconductance EA gain. Estimate phase margin obtained (it should be greater than 45) and repeat, modifying parameters, if necessary.
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Application details
L6726A
8.3
Soft Start time calculation
To calculate SS time (tSS), the following approximated equation can be used (CP<V OUT C F -------------- V OSC V IN = ------------------------------------------------I SS
t SS
The previous equation refers only to VOUT ramp up time. The time elapsed from the end of OC setting phase or COMP set free to the beginning of VOUT ramp up (see Figure 6) can be approximately estimated as follow:
C F 0.8V t delay = ----------------------I SS
Once calculated tSS, also the current delivered by the converter during SS to charge the output capacitor bank can be estimated:
C OUT V OUT I startup = --------------------------------t SS
8.4
Layout guidelines
L6726A provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 10) must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 10. Power connections (heavy lines)
VIN
UGATE PHASE
CIN L
L6726A
LGATE GND COUT LOAD
The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper number of vias when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection.
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L6726A
Application details Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. Gate traces and phase trace must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is recommended to minimize the distance between controller and power section. See Figure 11 for drivers current paths. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and Bootstrap capacitor) and loop compensation components as close to the device as practical. For over current programmability, place ROCSET close to the device and avoid leakage current paths on LGATE / OC pin, since the internal current source is only 10A Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big negative spikes on the PHASE pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase resistor in series to PHASE pin), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. It is then suggested in this case to limit this extra-charge by adding a small resistor in series to the bootstrap diode (RD in Figure 1). Figure 11. Drivers turn-on and turn-off paths
LS DRIVER VCC CGD RGATE LGATE CGS CDS RINT UGATE RPHASE PHASE CGS CDS RGATE RINT LS MOSFET HS DRIVER BOOT CGD HS MOSFET
GND
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Application details
L6726A
8.5
Embedding L6726A-based VRs...
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MBs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the VR can affect data integrity if additional layout guidelines are not followed. Few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): When reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. Keep safe guard distance between high current switching VR traces and data busses, especially if high-speed data busses, to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VR. Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive and Input voltage path (from input bulk capacitors and HS drain). Also GND connection must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data busses. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequence of the higher switching time, an increase in switching losses that must be considered in the thermal design of the system.
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L6726A
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data Table 6. SO-8 mechanical data
mm. Dim. Min A 1.35 Typ Max 1.75 Min 0.053 Typ inch
L6726A
Max 0.069
A1 A2 B C
D (1)
0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0.40
0.25 1.65 0.51 0.25 5.00 4.00
0.004 0.043 0.013 0.007 0.189 0.15 0.050
0.010 0.065 0.020 0.010 0.197 0.157
E e H h L k ddd
6.20 0.50 1.27
0.228 0.010 0.016
0.244 0.020 0.050
0 (min.), 8 (max.) 0.10 0.004
1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
Figure 12. Package dimensions
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L6726A
Revision history
10
Revision history
Table 7. Revision history
Date 16-Oct-2006 26-Oct-2006 30-Jul-2007 Revision 1 2 3 Initial release. Mechanical data dimensions updated Updated Figure 1 on page 4, tables 2, 3, 4, 5 Changes
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L6726A
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